1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a semiconductor memory device for reading stored data by selecting a word line, bit line, and virtual ground line to be connected to memory cells from which data will be read and selecting the memory cells.
2. Description of the Related Art
There is a conventional system of reading data from a memory cell by a nonvolatile semiconductor memory device such as a mask ROM (mask programmable Read Only Memory) or a flash memory by using the bit line and a virtual ground line. The method is described below by using a memory cell of a mask ROM having a simple memory cell structure. FIG. 8 shows a conceptual view of a reading system using the virtual ground line. In the case of this system, a bit line and a virtual ground line are alternately arranged along a column direction and word lines are arranged along a row direction on a memory cell array in which memory cells are arranged in the row direction and the column direction like a matrix, a memory cell transistor constituted by a MOSFET is set between a bit line and a virtual ground line adjacent to each other, and the drain and source electrodes of a memory cell transistor are connected to the bit line and the virtual ground line respectively. Moreover, the gate electrode of the memory cell transistor is connected to a word line. A plurality of memory cell transistors is connected to one word line to improve the area efficiency of the memory cell. In the case of these memory cell transistors, a threshold value is set when each of the transistors is fabricated (binary data is programmed for each memory cell) so as to serve as either of a transistor having a high threshold (off transistor having a threshold higher than a high-level potential of a word line serving as a gate electrode and to be normally turned off independently of the word-line potential) and a transistor having a low threshold (on transistor to be turned on when a word line potential is higher than the threshold). In the case of the reading operation, a word line, bit line, and virtual ground line to be connected to a transistor from which data will be read are selected, the selected bit line is charged to a predetermined potential, the selected virtual ground line is grounded to the ground potential, and the selected word line is set to the high level. The difference of currents of an on-transistor and off-transistor under the above state is sensed by a sensing circuit to determine the binary data stored in the memory cell.
In general, a hierarchical bit line system is known for a large-capacity semiconductor memory device as a system for reading data from these memory cell arrays at a high speed. A memory cell array according to the hierarchical bit line system is constituted by dividing a memory cell array into a plurality of blocks, using the bit line of each block as an auxiliary bit line (also referred to as local bit line), and connecting every a plurality of auxiliary bit lines of each block to a main bit line (also referred to as global bit line) through a block selection transistor. A bit line for selecting a memory cell is selected by selecting a main bit line and selecting an auxiliary bit line to be connected to the selected main bit line by the block selection transistor. The reading operation of the hierarchical bit line system is described below by referring to the accompanying drawings. FIG. 9 shows a configuration of a memory array cell according to the hierarchical bit line system. In the case of the memory cell array illustrated in FIG. 9, a virtual ground line also uses the same hierarchical structure as that of a bit line.
A group of memory cells using word lines WL0 to WLn present in a region held by control signals BKL1 and BKL2 and control signals BKL3 and BKL4 of a block selection transistor as gate electrodes is referred to as a block and a plurality of auxiliary bit lines (two bit lines in FIG. 9) SBi (i=even number) is connected to each main bit line MBi(i=even number) every block through a block selection transistor BK1-1 or the like in order to improve the area efficiency of a memory cell. High-speed reading is realized by accessing a memory cell every block through the main bit line.
As shown in FIG. 9, the block selection transistor BK1-1 or the like is selected by a bank selection line BKL1 or the like. A main bit line MB2 or the like is connected to an auxiliary bit line SB4 or the like through the block selection transistor BK11. The main bit line MBi (i=even number) of these memory arrays is connected to a charging circuit 22 and sensing circuit 23 or the like through a block selection circuit 20 for selecting a reading block and a charging/grounding election circuit 21 and the main virtual ground line MBi (i=odd number) of them is connected to a charging circuit 22 or ground line 24 or the like through the block selection circuit 20 and charging/grounding selection circuit 21. The charging/grounding selection circuit 21, charging circuit 22, and sensing circuit 23 may be connected to a plurality of block selection circuits 20.
The reading operation of the memory cell array circuit shown in FIG. 9 is described below. A case of selecting a memory cell transistor M4 and reading data from the M4 is assumed. The word line WL0 to be connected to the gate of the transistor M4 is set to the high level and other word lines (WLn) are set to the low level. The control signal BKL1 of a block selection transistor is set to the high level in order to turn on the block selection transistor BK1-1, the control signal BKL3 is set to the high level in order to turn on a block selection transistor BK3-2, and other control signals BKL2 and BKL4 are to the low level. Then, a current route (MB2)-(BK1-1)-(SB4) extending from a main bit line to a memory cell and a current route (SB5)-(BK3-2)-(MB3) extending from the memory cell to a main virtual ground line are formed on the transistor M4. When the transistor M4 is an on-transistor, by setting BSEL2 to the high level, VGSEL1 to the high level, BLOCKSEL1 to the high level, BSEL1 to the low level, and VGSEL2 to the lower level, the selected main bit line MB2 has a charging potential, the selected main virtual ground line MB3 has a ground potential, and current circulates through a route of (MB2)-(BK1-l)-(SB4)-(M4)-(SB5)-(BK3-2)-(MB3). By sensing a change or the like of the charging potential of the main bit line MB2 selected by the sensing circuit 24 connected from the selected main bit line MB2 through the transistor TR1 of the block selection circuit 20 and the transistor TR2 of the charging/grounding selection circuit 21, it is determined that the memory cell transistor M4 is an on-transistor.
However, when the memory cell transistor M4 is an off-transistor, transistors M3, M2, M1, and M0 or the like of an unselected memory cell in the same row as the transistor M4 are on-transistors, a current route via the transistors M3, M2, and M1 is formed even if, for example, the transistor M4 is an off-transistor because the word line WL0 serving as a gate line of each transistor is common. That is, when setting the selected main bit line MB2 to a charging potential, a transient current for charging the parasitic capacitance of a bit line or a virtual ground line connected to each memory cell circulates through a route of (MB2)-(BK1-1)-(SB4)-(M3)-(M2)-(M1) . . . . The current circulating through the current route is temporarily referred to as an alternate discharge current. As a result, a current route extended from a selected main bit line to each bit line or virtual ground line is formed as if the transistor M4 from which data will be read is an on-transistor though it is an off-transistor and the operation margin of an erroneous reading operation or reading operation is decreased. To prevent the erroneous reading operation or the like, a method of charging an unselected bit line and an unselected virtual ground line to a predetermined charging potential is conventionally used.
In the case of the circuit illustrated in FIG. 9, an unselected main bit line MB0 and unselected main virtual ground line MB1 are set to a charging potential. An auxiliary bit line SB0 and an auxiliary virtual ground line SB1 are set to a charging potential through a block selection transistor. Thus, even if the memory cell transistors M3, M2, M1, and M0 are on-transistors, an alternate discharge current for reading data from the memory cell transistor M4 disappears and a difference appears in the potential change of the selected main bit line MB2 when the transistor M4 is an on-transistor and an off-transistor and a stable memory-cell reading operation is realized.
However, the system of charging an unselected bit line and unselected virtual ground line for preventing an alternate discharge current decreases the reading operation margin on the other hand when a memory cell transistor from which data will be read is an on-transistor. To solve the problem of the operation margin decrease, Japanese Unexamined Patent Publication No. 10-11991 discloses an improved connection system for a memory cell transistor and a block selection transistor.
Then, it is described that a reading operation margin is decreased by a method of charging an unselected bit line and unselected virtual ground line for preventing an alternate discharge current by using the circuit shown in FIG. 9 as an example.
Though it is already described that the unselected main bit line MB0 and unselected main virtual ground line MB1 respectively have a charging potential because a selected main bit line becomes MB2 and a selected virtual ground line becomes MB3 to charge an unselected bit line and unselected virtual ground line when reading data from the memory cell transistor M4 similarly to the above description, the unselected main bit line MB4 and unselected main virtual ground line MB5 are further charged at the same time. When transistors M5, M6, M7, and M8 or the like in the same row as the transistor M4 are on-transistors, the unselected main bit line MB4 and unselected main virtual ground line MB5 extend through their respective block selection transistors, an auxiliary bit line SB8 and auxiliary virtual ground line SB9 respectively have a charging potential, and a current route extending to (SB8)-(M7)-(M6)-(M5)-(SB5) to charge the selected auxiliary virtual ground line SB5 is formed. The current circulating through the current route is temporarily referred to as alternate injection current. When the memory cell transistor M4 is an on-transistor, the alternate injection current raises the ground potential of the auxiliary virtual ground line SB5 and decreases the reading current of the selected main bit line MB2 circulating through (MB2)-(BK1-1)-(SB4)-(M4)-(SB5)-(BK3-2)-(MB3). The decrease of the reading current not only decreases the reading speed of a memory cell but also decreases a reading operation margin because a selected memory cell transistor may be erroneously read.
Moreover, it is general to read a plurality of memory cell transistors in parallel through one-time reading operation. In the case of the circuit illustrated in FIG. 9, however, it is possible to simultaneously read the memory cell transistor M4 and a memory cell transistor M12. The charging for preventing the current corresponding to the alternate discharge current of the transistor M4 for reading data from the memory cell transistor M12 corresponds to charging the unselected main bit line MB4 and unselected main virtual ground line MB5. Therefore, charging the unselected main bit line MB4 and unselected main virtual ground line MB5 decreases a reading current when the transistor M4 is an on-transistor. However, in the case of data reading when the transistor M12 is an off-transistor, charging the MB4 and MB5 is necessary.
It is possible to increase the number of unselected memory cell transistors present between the transistors M12 and M4, minimize charging an unselected bit line and unselected virtual ground line, and decrease the current corresponding to the alternate injection current flowing into the above-described selected bit line. However, the current corresponding to the alternate injection current is basically present. That is, when all the unselected memory cell transistors present between the transistors M12 and M4 are on-transistors, charging unselected bit lines and unselected virtual ground lines necessary for the data reading when the transistor M12 is an off-transistor decreases the reading current when the transistor M4 is an on-transistor by the current corresponding to the alternate injection current. However, the reading current when the transistor M4 is an on-transistor is still decreased.
The operation margin decrease measure disclosed in Japanese Unexamined Patent Publication No. 10-11991 also decreases the alternate injection current flowing into the selected bit line. Moreover, to restrict the control of these bit line and virtual ground line, the number of cells to be simultaneously read by the same word line is restricted and this greatly prevents the capacity of a memory cell array from increasing.